Submit your design!
Any teenager between the ages of 13 - 18 is allowed to submit an ASIC design to get on our shared chip and receive an FPGA board!
The one main restriction is no AI generating code. It's great at explaining concepts but relying on it to generate your HDL and tests is only hurting your own understanding of the concepts.
Submitting is quite simple:
- Create a GitHub repository with your chip design, I would suggest referencing any of the past chip GitHub repositories on the Tiny Tapeout website: https://tinytapeout.com/chips/. Your repository should have a complete design which means it's been simulated and appears to work in GTKWave, and passes all of the GitHub workflows, which should leave you with a physical preview of the logic gates for your chip, feel free to take a look at my first ASIC design: https://github.com/KaiPereira/SPI-Slave-ASIC.
- Create a write-up of your project and make it publicly available somewhere on the internet that's not GitHub, even share it around if you like. Learn how to create your write-up here.
- Submit to the form for an FPGA board here and once you've tested it on real hardware, submit for the shared chip here. If your design also needs a carrier board, you'll need to make one, but we'll give you a grant to buy the PCB too!